Welcome to Verilog-to-PyG – A framework for Graph Learning and Augmentation on RTL Designs

Important

V2PYG functions have been committed to master branch of abc.

• Source https://github.com/ycunxi/Verilog-to-PyG

• Make sure you compile ABC from Master branch https://github.com/berkeley-abc/abc``(``cd Verilog-to-PyG/abc;make -j4)

• Link ABC binary to the working folder

• (use ln -s your_path/abc/abc .; ln -s your_path/abc/abc.rc .)

Important

Check our paper “Verilog-to-PyG – A Framework for Graph Learning and Augmentation on RTL Designs”. Yingjie Li, Mingju Liu, Alan Mishchenko, Cunxi Yu. ACM/IEEE International Conference on Computer-Aided Design (ICCAD’23) at https://arxiv.org/pdf/2311.05722.pdf

Contact: Cunxi Yu (cunxiyu at umd.edu) (https://github.com/ycunxi), Yingjie Li (yingjiel at umd.edu)

• Installations
  • Packages

• Pre-Tutorials
  • Installations
  • Toy example verilog used in tutorials
• Tutorial - Example 1 - Boolean Networks
  • 2-bit Multiplier And-Inv-Graph (AIG) representation
    • Step 1: Process in ABC
    • Step 2: Check edgelist file written (mult-2b.el)
    • Step 3: Check the topology of the netlist
• Tutorial - Example 2 - Mapped netlist
  • 2-bit Multiplier technology mapped netlist representation
    • Step 1: Process in ABC
    • Step 2: Check edgelist file written (mult-2b.el)
    • Step 3: Check the topology of the netlist
• Tutorial - Example 3 - Sequential
  • 2-bit Sequential Multiplier in AIG representation
    • Step 1: Process in ABC
    • Step 2: Check netlist
    • Step 3: Check the edgelist
    • Step 3: Check the topology of the netlist
• Tutorial - Example 4 - RTL augmentaion
  • And-Inv-Graph (AIG) based RTL augmentaion
    • Step 1: aigaug - AIG RTL augmentaion
    • Step 2: Check functional equivalence using SAT-based equivalence checker